1. Field of the Invention
The present invention relates to a method and an integrated circuit (IC) for detecting capacitance variation, and more particularly to a method and an IC that are capable of detecting capacitance variation using two time divisional frequencies, thereby enhancing sensitivity of detecting capacitance variation.
2. Description of the Related Art
A prior art integrated circuit of detecting capacitance variation is implemented to compare variation of detection frequency varied according to capacitance variation with a reference frequency and to output the detection frequency if the difference as the comparison result is over a predetermined value. Owing to time delay components of a charging/discharging control unit of a frequency generator generating a detection frequency, the detection frequency cannot be substantially generated in proportion to a capacitance variation. Therefore a lot of errors are produced when a relatively small capacitance variation is detected.
FIG. 1 is a circuit describing a prior art single frequency generator. Referring to FIG. 1, a target capacitor is installed in an input unit of an integrated circuit (IC) for detecting capacitance variation such that capacitance variation of the target capacitor can be detected. Before performing the detection, we assume that capacitance of the target capacitor is denoted as Cs, a constant current for charging/discharging the target capacitor is denoted as Is, parasitic capacitance generated in arrangement wires of the input unit is denoted as Cp, and td denotes time delay of the charging/discharging control unit, in which the time delay td includes switch delay components of a Schmitt trigger SCHMITT_A, an inverter INV_1A, PMOS transistors PM1˜PM3 and NMOS transistors NM1˜NM3. A time (period), Ta, means a time taken from when the target capacitor starts charging until its positive lead level reaches an input level of the Schmitt trigger SCHMIT_A, Vth (Vth=Vb−Va), and is expressed by the following equation.
                              1          /          fa                =                  Ta          =                      td            +                                          2                ⁢                                  Vth                  ⁡                                      (                                          Cs                      +                      Cp                                        )                                                              Is                                                          (        1        )            
In the case that the capacitance Cs of the target capacitor installed in the input unit is changed into capacitance Cs+Cx, a time (period), Ta′, means a time taken from when the target capacitor starts charging until its positive lead level reaches Vth and is expressed by the following equation.
                              1          /                      fa            ′                          =                              Ta            ′                    =                      td            +                                          2                ⁢                                  Vth                  ⁡                                      (                                          Cs                      +                      Cp                      +                      Cx                                        )                                                              Is                                                          (        2        )            
Therefore, the variation of the period is expressed by the following equation.
                                                        Ta              ′                        -            Ta                    Ta                =                  Cx                                    (                              Cs                +                Cp                            )                        +                                          (                                                      Is                    /                    2                                    ⁢                  Vth                                )                            ·              td                                                          (        3        )            
From the above equations, unless the time delay td of the charging/discharging control unit for capacitance variation Cx becomes sufficiently small, variation of a detection frequency fa for the capacitance variation Cx becomes small such that precision of its sensitivity can be decreased. Especially, if the detection frequency increases in order to prevent external noises, the prior art device can be largely affected by the components of the time delay td.
Therefore, the prior art IC has disadvantages in that, due to the time delay component of the charging/discharging control unit, variation of the detection frequency according to the capacitance variation is relatively small and thusly variation of small capacitance cannot be detected.